Highly integrated semiconductor memory chips to reduce size meant longer test time for evaluating the memory characteristics. To reduce the test time, a parallel test or testing a plurality of bits at a time is used.
For example, to perform a parallel test on a semiconductor memory chip with 1M as a unit, four bits would be tested at the same time. For a semiconductor memory chip with 4M as a unit, eight bits would be tested at the same time. For a semiconductor memory chip with 16M as a unit, 16 or more bits would be tested at the same time.
In addition, a semiconductor memory chip includes a plurality of data pads through which data are inputted and outputted. Also, the semiconductor memory chip includes a plurality of data strobe signal pads which transmit data strobe signals used in capturing the data at the receiver. When the known test is performed, the data signals and the data strobe signals are applied only to some data pads and data strobe signal pads selected among the plurality of data pads and data strobe signal pads included in the semiconductor memory chip. That is, in the known test, the data outputted through the selected data pads may be verified to check the characteristics of output drivers coupled to the selected data pads.
Therefore, the characteristics of output drivers coupled to unselected data pads among the plurality of data pads included in the semiconductor memory chip cannot be checked through the known test method.